A computer system is generally comprised of several component parts including a processor, random access memory, a data bus, and other peripheral devices and components. The processor accesses, modifies, and writes data to random access memory. The data contained in random access memory is transferred to the processor through the data bus. One type of random access memory is dynamic random access memory (DRAM). As computer processor speeds increase, faster random access memory is needed to fully realize the potential of faster processor chips. One solution for faster random access memory is synchronous DRAM (SDRAM). SDRAM is tied to a system clock and is designed to be able to read or write from memory in burst mode (after the initial read or write latency) at one clock cycle per access (zero wait states) at memory bus speeds up to 100 MHz. However, current computer processor speeds often exceed the capability of SDRAM to provide data from memory.
Double Data Rate Synchronous Dynamic Random Access Memory (DDR-SDRAM) addresses the need for faster random access memory. DDR-SDRAM is similar in function to regular SDRAM, but it doubles the bandwidth of the memory by transferring data twice per cycle, on both the rising and falling edges of the clock signal. DDR-SDRAM returns a strobe signal synchronously with data signals. The strobe signal is related to the memory clock signal and indicates when valid data is ready for transfer from the DDR-SDRAM. Data signals are available on both the rising edge of the strobe signal and the falling edge of the strobe signal. Thus, two data signals are available with each clock cycle of a memory clock used for the DDR-SDRAM. In order to use DDR-SDRAM, the computer processor needs to synchronize the data coming from the DDR-SDRAM with the internal core clock of the computer processor chip. The internal core clock is often used to clock the data bus across which the data signals from the DDR-SDRAM are sent to the computer processor chip.
DDR-SDRAM may use a variety of DRAM configurations such as 4-bit DRAMs, 8-bit DRAMs, 16-bit DRAMs, or 32-bit DRAMs. Conventional synchronizers for DDR-SDRAM are usually designed for a single DDR-SDRAM configuration. Due to variations in DDR-SDRAM, the computer processor chip, and mother boards, strobe signals and data signals may not arrive together at the synchronizer. Conventional synchronizers for DDR-SDRAM are usually designed for a particular situation where the strobe signal and data signals do not arrive together. Therefore, it is desirable to provide a configurable synchronizer for DDR-SDRAM that allows the synchronizer to be optimized for various implementations.